dwn-fpga-study — FPGA Design-Space Exploration for Weightless Neural Networks
A 77-build automated sweep across width, encoder resolution, fan-in, depth, and clock target — built on the dwn2rtl compiler — to find the actual accuracy/area frontier instead of guessing at it.
- 77
- Builds swept
- −40% (−0.24 pts acc.)
- LUT savings
- 58.6 → 100.9 MHz
- Fmax
The problem
Having a working compiler (dwn2rtl) only gets you a way to build a design — it doesn’t tell you which point in the width/depth/ encoder-resolution space is actually worth building. Answering that requires running the compiler dozens of times over and comparing real synthesis results, not guessing from intuition.
Approach
An automated sweep harness drives dwn2rtl across width, encoder resolution, fan-in, depth, and clock target — running synthesis and place-and-route for each generated design, then parsing the reports back into a comparable dataset. Configurable pipeline stages let the same design trade latency for Fmax without a rewrite, so timing tradeoffs are part of the sweep too, not a separate manual step afterward.
What broke
Running synthesis and place-and-route 77 times by hand isn’t viable — the entire value of this project is in the automation, so the build-and- report-parse cycle had to be scripted end to end and trusted to run unattended. That investment paid off directly: a 4× smaller encoder cut LUT usage 40% for a 0.24-point accuracy cost, a tradeoff that would have been expensive to discover by hand-tuning one design at a time.
Results
| Change | Effect |
|---|---|
| 4× smaller encoder | −40% LUT usage, −0.24 accuracy points |
| Configurable pipeline depth | Fmax 58.6 MHz → 100.9 MHz on a 1,600-node design |
| Full sweep | 77/77 generated designs verified bit-exact (via dwn2rtl’s own checks) |
What I’d do differently
Pending — this project’s retrospective wasn’t in the source material this case study was drafted from. Krithik: what would you change if you did this again?