dwn2rtl — Checkpoint-to-Verilog Compiler for Weightless Neural Networks

The problem

Weightless neural networks (WNNs) replace multiply-accumulate neurons with lookup tables — which should map almost natively onto an FPGA’s own LUT fabric. “Almost natively” still leaves a real gap: getting a trained model’s weights out of a checkpoint and into synthesizable RTL without hand translation, and trusting that the generated hardware actually computes what the checkpoint says it should.

Approach

dwn2rtl is a pip-installable compiler that takes a trained WNN checkpoint and emits Verilog directly, mapping each 6-input neuron one-to-one onto a LUT6 primitive — no synthesis inference needed to recover the intended structure, because the structure is generated correctly the first time. The input datapath is quantized to Q3.12 fixed-point.

What broke

Bit-exactness was the hard requirement, not a nice-to-have: a compiler that’s usually right isn’t good enough when the whole point is generating trustworthy hardware from a checkpoint. Every design the compiler produces is checked bit-exact against a NumPy golden model, and separately verified on-board with 166,000 vectors streamed over UART — matching in simulation isn’t the same guarantee as matching after synthesis and place-and-route on real silicon, so both checks run independently.

Results

A working checkpoint-to-Verilog compiler, verified bit-exact in simulation and on real hardware. It’s also the foundation dwn-fpga-study is built on — the compiler had to be trustworthy before a 77-build design-space sweep on top of it meant anything.

What I’d do differently

Pending — this project’s retrospective wasn’t in the source material this case study was drafted from. Krithik: what would you change if you did this again?